1. Field of the Invention
The present invention relates to current conveyor circuits, and in particular, to current conveyor circuits operating at low voltages with high power supply noise.
2. Description of the Related Art
Referring to FIG. 1, a conventional gain-boosting circuit, often referred to as a current conveyor circuit, includes two transistors, P-type metal oxide semiconductor field effect transistors (P-MOSFETs) M1, M2, and three current sources I1, I2, I3, all interconnected substantially as shown. Referring to FIGS. 1A and 1B, in accordance with well-known current source circuit design techniques, the upper current source I1 can be implemented using a P-type MOSFET P1 with a bias voltage Vbiasp applied at its gate electrode to generate its output current I1. Similarly, each of the lower current sources I2, I3 can be implemented as an N-type MOSFET N1 with an appropriate bias voltage Vbiasn applied at its gate electrode to generate its current output I2, I3.
In such a current conveyor circuit, an input current Iin is applied at the source electrode of transistor M1, which conveys such current to its drain electrode to be made available as the output current Iout. The circuit node at the source electrode of transistor M1 provides a low impedance path for the input current Iin, while the drain electrode of transistor M1 provides a high output impedance, thereby providing good isolation between the input (source electrode) and output (drain electrode). By including transistor M2 with its connections as shown the input impedance path for the input current Iin is reduced even further. The high impedance node at the drain electrode of transistor M2 (and gate electrode of transistor M1) and the resultant negative feedback loop can be compensated by connecting a shunt capacitance C1, e.g., between such node and the lower power supply electrode VSS/GND.
A problem arises when such a circuit is used in a large system where a significant amount of noise can appear within the power supply, particularly within the power supply reference, or ground, connection. Often such power supply noise can be quite large in magnitude as compared to the power supply voltage VDD which is often very low (e.g., 1.6 volts). As is evident from the circuit connections, the voltage V2 at the input electrode is one gate-to-source voltage VGS below the power supply voltage VDD, i.e., VDD-VGS. Accordingly, the voltage V1 at the gate electrode of the output transistor M1 is lower by one additional gate-to-source voltage VGS, i.e., VDD−2*VGS.
This makes the voltage across current source I3 also equal to VDD−2*VGS. In an integrated circuit fabricated using a typical 0.18 micron process, the threshold voltage VT of the transistors M1, M2 is approximately 0.45 volt, while the saturation voltage VDSAT of the transistors within a good region of operation is approximately 0.2 volt. With a supply voltage of 1.6 volt, this makes the voltage across current source I3 equal to VDD−2*VGS=1.6−2*0.45=1.6−1.3=0.3 volt.
If this current source I3 is a simple N-MOSFET current source (e.g., transistor N1 in FIG. 1B) operating with a minimum saturation voltage VDSAT of 0.2 volt, then it is operating with a 0.1 volt margin. However, if the power supply noise, via the ground connection VSS/GND, exceeds this margin of 0.1 volt, the device forming this current source I3 will fall out of saturation, thereby allowing the noise voltage to modulate the voltage V1 at the gate electrode of the output transistor M1. As a result, the noise becomes coupled into the output current Iout.